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-Address/E-mail-Courses
-Education
-Research Interests
-Experiences-Professional Activities-Awards & Honors
-Publications
-Research Project-Advisees
-Summary     
         

               

       Lee, Yu-Min
Associate Professor

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Address/E-mail
Address             1001 University Road, Hsinchu, Taiwan 300, ROC
                          Department of Electrical Engineering, National Chiao Tung University
, Taiwan
Email                  yumin@nctu.edu.tw
Office               ED 835  (Phone 886-3-513-1274)
FAX No.             886-3-517-0116  
Laboratory         ED 718  (Phone 886-3-571-2121 ext 54586)
Lab Home Page   http://vlsi-eda.cm.nctu.edu.tw/


Courses
http://vlsi-eda.cm.nctu.edu.tw/course/index.html

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Education
Ph.D
University of Wisconsin-Madison, USA ˇV August 2003
Major: Electrical and Computer Engineering
Thesis: Efficient Chip-Level Power Grid Networks Simulation and Optimization Techniques
Advisor: Professor Charlie Chung-Ping Chen


M.S.
National Chiao Tung University, Hsinchu, Taiwan ˇV June 1993
Major: Communication Engineering
Thesis: Blind Equalization for High Order QAM Signals
Advisor: Professor Ta-Sung Lee

B.S.
National Chiao Tung University, Hsinchu, Taiwan ˇV June 1991
Major: Communication Engineering


Research Interests
ˇ´ Computer-aided design of VLSI
ˇ´ Circuit/thermal/electro-thermal analysis and simulation  
ˇ´ Interconnect analysis and optimization
ˇ´ Design for manufacturability

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Experiences
August 2003ˇVpresent               Assistant Professor
                                                National Chiao Tung University, Hsinchu, Taiwan
June 2000ˇVAugust 2003           Research Assistant
                                                University of Wisconsin-Madison, USA
June 2001ˇVAugust 2001            Summer Intern
                                                 Intel Corp., Austin, Texas, USA
September 1999ˇVJune 2000     Teaching Assistant
                                                 University of Wisconsin-Madison, USA
June 1995ˇVOctober 1995          Senior Engineer
                                                 ZyXEL Communications Corp., Hsinchu, Taiwan
September 1991ˇVJune 1993       Research Assistant
                                                 National Chiao Tung University, Hsinchu, Taiwan
September 1991ˇVJune 1993      Teaching Assistant
                                                 National Chiao Tung University, Hsinchu, Taiwan

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Professional Activities
Technical Program Committee Member / Session Chair
ˇ´ ACM/IEEE Asia and South Pacific Design Automation Conference, 2009 and 2010
ˇ´ Workshop on Synthesis & System Integration of Mixed Information Technologies, 2009
ˇ´ VLSI Design/CAD Symposium, Taiwan, 2006, 2008 and 2009
ˇ´ MOE IC/CAD Contest, Taiwan, 2004-present
ˇ´ Review Committee Member of IEEE International Symposium on Quality Electronic Design, 2007ˇV2009
ˇ´ Invited Session Co-Chair, VLSI Design/CAD Symposium, Taiwan, 2004, 2005 and 2008

Reviewer for Professional Submittals
ˇ´ IEEE Transactions on Very Large Scale Integration Systems (TVLSI)
ˇ´ IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)
ˇ´ ACM Transactions on Design Automation of Electronic Systems (TODAES)
ˇ´ IEEE Circuits and System Magazine
ˇ´ VLSI Design Journal
ˇ´ Chung Hua Journal of Science and Engineering

Society Member
ˇ´ Circuits and Systems Society of IEEE
ˇ´ Professional Member of ACM
ˇ´ Taiwan IC Design Society (TICD)
ˇ´ Founding Member of Electronic Design Automation Forum (EDAF), Taiwan

Invited Talks
ˇ´ Title: Thermal Simulation of VLSI Designs
   Department of Electrical Engineering
   National Central University, November 10, 2008
ˇ´ Title: Techniques for Power Grid Analysis
   Department of Applied Mathematics
   National Chiao Tung University, November 29, 2007
ˇ´ Title: Power Delivery Network Analysis and Thermal Simulator Techniques
   MOE EDA Forum, Taiwan, March 3, 2006

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Awards & Honors
ˇ´ Marquis Whoˇ¦s Who in the World, 2009 edition and selected for 2010 edition
ˇ´ Excellent Undergraduate Advisor, National Chiao Tung University, 2008
ˇ´ The 1st Place, supervision for the IC/CAD Contest 2007 held by Ministry of Education
   (MOE), Taiwan.
ˇ´ ACM International Symposium on Physical Design Best Paper Award, 2003
ˇ´ Harold A. Peterson First Place Graduate Student Paper Award, Electrical and Computer
   Engineering Department, University of Wisconsin-Madison, 2003

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Publications 
Journal
[1] Pei-Yu Huang and Yu-Min Lee, ˇ§Full-chip thermal analysis for the early design stage via generalized integral transforms,ˇ¨ IEEE Transactions on Very Large Scale Integration Systems, vol. 17, no. 5, pp. 613ˇV626, May, 2009.

[2] Yu-Min Lee and Po-Yi Chiang, ˇ§Effective sleep transistor sizing algorithm for leakage power reduction,ˇ¨ to appear in International Journal of Electrical Engineering, 2009.

[3] Pei-Yu Huang and Yu-Min Lee, ˇ§Hierarchical power delivery network analysis via bipartite Markov chains,ˇ¨ International Journal of Electrical Engineering, vol. 16, no. 2, pp. 121ˇV132, May, 2009.
 
[4] Yu-Min Lee, Yahong Cao, Tsung-Hao Chen, Janet Wang and Charlie Chung-Ping Chen, "HiPRIME: Hierarchical and Passivity Preserved Interconnect Macromodeling Engine for RLKC Power Delivery," IEEE Transactions on Computer-Aided Design of Integrated Circuits And Systems (TCAD), Vol. 24, No. 6, pp. 797-806, June, 2005.

[5] Yu-Min Lee and Charlie Chung-Ping Chen, "The Power Grid Transient Simulation in Linear Time Based on 3D Alternating-Direction-Implicit Method", IEEE Trans. Computer-Aided Design of Integrated Circuits And Systems (TCAD), Vol. 22, No. 11, pp. 1545-1550, November, 2003.

[6] Yu-Min Lee and Charlie Chung-Ping Chen, "Power Grid Transient Simulation in Linear Time Based on Transmission-Line-Modeling Alternating-Direction-Implicit Method", IEEE Trans. Computer-Aided Design of Integrated Circuits And Systems (TCAD), Vol. 21, No. 11, pp. 1343 -1352, November, 2002.

[7] Yu-Min Lee, Charlie Chung-Ping Chen, and D. F. Wong, "Optimal Wire-sizing Function under the Elmore Delay Model with Bounded Wiresizes", IEEE Trans. Circuits & Systems-I (TCAS-I) Vol. 49, No. 11, pp. 1671--1677, Nov. 2002.

[8] Yu-Min Lee, Charlie Chung-Ping Chen, Yao-Wen Chang, and D. F. Wong,ˇ§Simultaneous buffer-sizing and wire-sizing for clock trees based on Lagrangian relaxationˇ¨, VLSI Design Journal, vol. 15, no. 3, pp. 587-594, 2002.

[9] Ta-Sung Lee, Yu-min Lee,ˇ§Phase coherent blind equalization for high order QAM signalsˇ¨, Journal of the Chinese Institute of Electrical Engineering, vol.1, no.1, 1994.

International Conference

[1] Pei-Yu Huang, Jia-Hong Wu, and Yu-Min Lee, ˇ§Stochastic thermal simulation considering spatial correlated within-die process variations,ˇ¨ Proc. of IEEE Asia South Pacific Design Automation Conference, pp. 31ˇV36, January 2009.

[2] Shih-An Yu, Pei-Yu Huang, and Yu-Min Lee, ˇ§A multiple supply voltage based power reduction method in 3-D ICs considering process variations and thermal effects,ˇ¨ Prof. of IEEE Asia South Pacific Design Automation Conference, pp. 55ˇV60, January 2009.

[3] Cheok-Kei Lei, Po-Yi Chiang, and Yu-Min Lee, ˇ§Post-routing redundant via insertion with wire spreading capability,ˇ¨ Proc. of IEEE Asia South Pacific Design Automation Conference, pp. 468ˇV473, January 2009.

[4] Jin-Tai Yan, Zhi-Wei Chen, Bo-Yi Chiang, and Yu-Min Lee, ˇ§Timing-constrained yield-driven redundant via insertion,ˇ¨ Proc. of IEEE Asia Pacific Conference on Circuits and Systems, pp. 1688ˇV1691, December 2008.

[5] Pei-Yu Huang, Chih-Kang Lin, and Yu-Min Lee, "Full-Chip Thermal Analysis for the Early Design Stage via Generalized Integral Transforms", Asia South Pacific Design Automation Conference (ASP-DAC) 2008.

[6] Pei-Yu Huang, Chih-Kang Lin, and Yu-Min Lee, "Hierarchical Power Delivery Network Analysis Using Markov Chains", IEEE International SOC Conference (SOCC) 2007

[7] Yu-Min Lee, Huan-Yu Chou, Pei-Yu Huang, "An Aggregation-based Algebraic Multigrid Method for Power Grid Analysis", 8th International Symposium on Quality Electronic Design (ISQEDˇ¦07)

[8] Pei-Yu Huang,Yu-Min Lee, Jeng-Liang Tsai, and Charlie Chung-Ping Chen, "Simultaneous area minimization and decaps insertion for power delivery network using adjoint sensitivity analysis with IEKS method", International Symposium on Circuits and Systems (ISCAS) 2006, 2006-05

[9] Ting-Yuan Wang, Yu-Min Lee, and Charlie Chung-Ping Chen,ˇ§3D Thermal-ADI: an efficient chip-level transient thermal simulatorˇ¨, International Symposium on Physical Design (ISPD) 2003 (best paper award).

[10] Yu-Min Lee, Charlie Chung-Ping Chen,ˇ§The power grid transient simulation in linear time based on 3D alternating-direction-implicit methodˇ¨, Design, Automation and Test in Europe (DATE) 2003.

[11] Yu-Min Lee, Charlie Chung-Ping Chen,ˇ§A hierarchical analysis methodology for chip-level power delivery with realizable model reductionˇ¨, Asia South Pacific Design Automation Conference (ASP-DAC) 2003.

[12] Yahong Cao, Yu-Min Lee, Tsung-Hao Chen, and Charlie Chung-Ping Chen,ˇ§HiPRIME: Hierarchical and passivity reserved interconnect macromodeling engine for RLKC power deliveryˇ¨, Design Automation Conference (DAC) 2002.

[13] Yu-Min Lee, Charlie Chung-Ping Chen,ˇ§Power grid transient simulation in linear time based on transmission-line-modeling alternating-direction-implicit methodˇ¨, International Conference on Computer Aided Design (ICCAD) 2001.This work was cited by the article "Analog modeling gets close but no cigar." in the EETimes weekly, December 6,2001.

[14] Saisanthosh Balakrishnan, Jong Hyuk Park, Hyungsuk Kim, Yu-Min Lee, and Charlie Chung-Ping Chen,ˇ§Linear time hierarchical capacitance extraction without multiple expansionˇ¨, International Conference on Computer Design (ICCD) 2001.

[15] Yu-Min Lee, Hing Yin Lai, Charlie Chung-Ping Chen,ˇ§Optimal spacing and capacitance padding for general clock structuresˇ¨, Asia South Pacific Design Automation Conference (ASP-DAC) 2001.

[16] Yu-Min Lee, Charlie Chung-Ping Chen,ˇ§Hierarchical model order reduction for signal-integrity driven interconnect synthesisˇ¨, Great Lake Symposium on VLSI (GLSVLSI) 2000

Domestic Conference

[1] Huai-Chung Chang, Pei-Yu Huang, Ting-Jung Li, and Yu-Min Lee, ˇ§Thermal yield estimation using statistical electro-thermal simulator,ˇ¨ Proc. of the 20th VLSI Design/CAD Symposium, August 2009.

[2] Tsung-You Wu and Yu-Min Lee, ˇ§Fast Legalize: Legalization with minimal disturbance for standard cell design,ˇ¨ Proc. of the 20th VLSI Design/CAD Symposium, August 2009.

[3] Cheok-Kei Lei, Bo-Yi Chiang, and Yu-Min Lee, ˇ§An efficient redundant via insertion with wire pushing capability,ˇ¨ Proc. of the 19th VLSI Design/CAD Symposium, August 2008.

[4] Shih-An Yu, Pei-Yu Huang, and Yu-Min Lee, ˇ§Power optimization in 3D ICs considering process variations and thermal effect,ˇ¨ Proc. of the 19th VLSI Design/CAD Symposium, August 2008.

[5] Pei-Yu Huang, Jia-Hong Wu, Yu-Min Lee, and Huai-Chung Chang, ˇ§Stochastic thermal simulation considering with-in die process variations,ˇ¨ Proc. of the 19th VLSI Design/CAD Symposium, August 2008.

[6] Huan-Yu Chou and Yu-Min Lee, ˇ§An aggregation-based algebraic multigrid method with application to on-chip power network analysis,ˇ¨ Proc. of 16th VLSI Design/CAD Symposium, August 2005.

[7] Simon Yi-Hung Chen, Zhe-Yu Lin ,Yu-Min Lee,ˇ§LPGC : A Novel Low Power Driven Placement Algorithm Based on Optimal Gated Clock Topologyˇ¨ in Proceedings of the 16th VLSI Design/CAD Symposium, 2005.

[8] Yu-Min Lee, Jeng-Liang Tsai, and Charlie Chung-Ping Chen, ˇ§Simultaneous Area Minimization and Decaps Insertion for Power Delivery Network Using Adjoint Sensitivity Analysis with IEKS Methodˇ¨ in Proceedings of the 14th VLSI Design/CAD Symposium, 2003.

International Workshop
[1]
Pei-Yu Huang, Chih-Kang Lin, and Yu-Min Lee, ˇ§Full-chip thermal analysis via generalized integral transforms,ˇ¨ Workshop on Synthesis and System Integration of Mixed Information Technologies, pp 302ˇV309, October 2007.

[2] Yih-Lang Lin, Pei-Yu Huang, Chih-Hong Hwang, and Yu-Min Lee, ˇ§Performance-and congestion-driven multilevel router,ˇ¨ Workshop on Synthesis and System Integration of Mixed Information Technologies, pp. 439ˇV445, April 2006.

[3] Pei-Yu Huang, Chih-Hong Hwang, Po-Han Lai, and Yu-Min Lee, ˇ§Hierarchical power deliver network analysis via bipartite Markov chain,ˇ¨ Workshop on Synthesis and System Integration of Mixed Information Technologies, pp. 189ˇV196, April 2006.

[4] Cheng-Hsuan Chiu, Yu-Chan Chang, Pei-Yu Huang, Chih-Hong Hwang, and Yu-Min Lee, ˇ§Crosstalk-driven placement with considering on-chip mutual inductance and RLC noise,ˇ¨Workshop on Synthesis and System Integration of Mixed Information Technologies, pp. 429ˇV433, April 2006.

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Research Project
Ongoing Projects
1. Process Variations Aware Interconnect Modeling, Timing Analysis and Optimization (2/3) (Amount: NTD$1,122,000; Aug. 2007 ~ Jul. 2008, NSC)

2. Compact Thermal Modeling and Efficient Thermal Simulation for Hot Spots Verifications of Modern IC Designs (3/3) (Amount: NTD$1,229,000; Aug. 2007 ~ Jul. 2008, NSC)

Completed Projects

1. Process Variations Aware Interconnect Modeling, Timing Analysis and Optimization (1/3) (Amount: NTD$1,107,000; Aug. 2006 ~ Jul. 2007, NSC)

2. Compact Thermal Modeling and Efficient Thermal Simulation for Hot Spots Verifications of Modern IC Designs (2/3) (Amount: NTD$1,229,000; Aug. 2006 ~ Jul. 2007, NSC)

3. Compact Thermal Modeling and Efficient Thermal Simulation for Hot Spots Verifications of Modern IC Designs (1/3) (Amount: NTD$1,076,000; Aug. 2005 ~ Jul. 2006, NSC)

4. Power Delivery Network Analysis with Hierarchical Model Order Reduction Techniques (3/3) (Amount: NTD$894,000; Aug. 2005 ~ Jul. 2006, NSC)

5. Power Delivery Network Analysis with Hierarchical Model Order Reduction Techniques (2/3) (Amount: NTD$882,000; Aug. 2004 ~ Jul. 2005, NSC)

6. Power Delivery Network Analysis with Hierarchical Model Order Reduction Techniques (1/3) (Amount: NTD$612,700; Nov. 2003 ~ Jul. 2004, NSC)

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Advisees
Doctoral Student Advisees
Chi-Wen Pan                2009ˇVpresent
Po-Yi Chiang                2007ˇVpresent
Pei-Yu Huang               2006ˇVpresent

Master Student Advisees
Chih-Sheng Wang        2009ˇVpresent
Shu-Han Whi               2008ˇVpresent
Ting-Jung Li                2008ˇVpresent
Chiao-Lin Cheng           2008ˇVpresent
Cheng-Chung Chien      2005ˇVpresent

Masters Degree Research Supervisor
Huai-Chung Chang
ˇ§An electro-thermal simulator considering process variations with high compatibility of power modelˇ¨, 2009

Tsung-You Wu
ˇ§FastLegalize: Legalization for standard cell based design with minimal disturbanceˇ¨, 2009 Shian-Je Shiu ˇ§A novel and fast sleep transistor sizing algorithm by using integral sensitivityˇ¨, 2009

Bing-Hsing Su
ˇ§Bootstrap confidence intervals as an approach to model within-die spatial correlation under process variationsˇ¨, 2009, currently working for TSMC

Cheok-Kei Lei
ˇ§An efficient redundant via insertion method with wire pushing capabilityˇ¨, 2008, currently working for TSMC

Shih-An Yu
ˇ§Power optimization in 3D ICs considering process variations and thermal effectˇ¨, 2008, currently working for Synopsys Taiwan

Jia-Hong Wu
ˇ§Stochastic thermal simulation considering within-die spatial correlation under process variationsˇ¨, 2007, currently working for TSMC

Zhe-Yu Lin
ˇ§A multilevel low power clock network driven placementˇ¨, 2006, currently working for Synopsys Taiwan

Huan-Yu Chou
ˇ§An aggregation-based algebraic multigrid method with application to on-chip power distribution network analysisˇ¨, 2006, currently working for Faraday Technology

Chen-Hsuan Chiu
ˇ§Crosstalk-driven placement with on-chip mutual inductance and RLC noise considerationsˇ¨, 2005, currently working for ITRI Electronics Research & Service Organization

Yih-Lang Lin
ˇ§Performance- and congestion- driven multilevel routerˇ¨, 2005, currently working for eMemory Technology

Yi-Hung Chen
ˇ§LPGC: A novel low power driven placement algorithm based on optimal gated clock topologyˇ¨, 2005, currently working for SpringSoft Inc.

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Summary

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