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Address/E-mail
Address
1001 University Road, Hsinchu, Taiwan 300, ROC
Department
of Electrical Engineering, National Chiao Tung University,
Taiwan
Email
yumin@nctu.edu.tw
Office ED 835 (Phone
886-3-513-1274)
FAX No.
886-3-517-0116
Laboratory ED 718
(Phone 886-3-571-2121 ext 54586)
Lab Home Page
http://vlsi-eda.cm.nctu.edu.tw/
Courses
http://vlsi-eda.cm.nctu.edu.tw/course/index.html
¡@
Education
Ph.D
University of Wisconsin-Madison, USA ¡V August 2003
Major: Electrical and Computer Engineering
Thesis: Efficient Chip-Level Power Grid Networks Simulation and
Optimization Techniques
Advisor: Professor Charlie Chung-Ping Chen
M.S.
National Chiao Tung University, Hsinchu, Taiwan ¡V June 1993
Major: Communication Engineering
Thesis: Blind Equalization for High Order QAM Signals
Advisor: Professor Ta-Sung Lee
B.S.
National Chiao Tung University, Hsinchu, Taiwan ¡V June 1991
Major: Communication Engineering
Research Interests
¡´
Computer-aided design of VLSI
¡´
Circuit/thermal/electro-thermal analysis and simulation
¡´
Interconnect analysis and optimization
¡´
Design for manufacturability
¡@
Experiences
August 2003¡Vpresent
Assistant Professor
National Chiao Tung University, Hsinchu, Taiwan
June 2000¡VAugust 2003
Research Assistant
University of Wisconsin-Madison, USA
June 2001¡VAugust 2001
Summer Intern
Intel Corp., Austin, Texas, USA
September 1999¡VJune 2000 Teaching
Assistant
University of Wisconsin-Madison, USA
June 1995¡VOctober 1995
Senior Engineer
ZyXEL Communications Corp., Hsinchu, Taiwan
September 1991¡VJune 1993
Research Assistant
National Chiao Tung University, Hsinchu, Taiwan
September 1991¡VJune 1993 Teaching
Assistant
National Chiao Tung University, Hsinchu, Taiwan
¡@
Professional Activities
Technical Program Committee Member / Session Chair
¡´ ACM/IEEE Asia and South Pacific Design Automation Conference,
2009 and 2010
¡´ Workshop on Synthesis & System Integration of Mixed
Information Technologies, 2009
¡´ VLSI Design/CAD Symposium, Taiwan, 2006, 2008 and 2009
¡´ MOE IC/CAD Contest, Taiwan, 2004-present
¡´ Review Committee Member of IEEE International Symposium on
Quality Electronic Design, 2007¡V2009
¡´ Invited Session Co-Chair, VLSI Design/CAD Symposium, Taiwan,
2004, 2005 and 2008
Reviewer for Professional Submittals
¡´ IEEE Transactions on Very Large Scale Integration Systems (TVLSI)
¡´ IEEE Transactions on Computer-Aided Design of Integrated
Circuits and Systems (TCAD)
¡´ ACM Transactions on Design Automation of Electronic Systems (TODAES)
¡´ IEEE Circuits and System Magazine
¡´ VLSI Design Journal
¡´ Chung Hua Journal of Science and Engineering
Society Member
¡´ Circuits and Systems Society of IEEE
¡´ Professional Member of ACM
¡´ Taiwan IC Design Society (TICD)
¡´ Founding Member of Electronic Design Automation Forum (EDAF),
Taiwan
Invited Talks
¡´ Title: Thermal Simulation of VLSI Designs
Department of Electrical Engineering
National Central University, November 10, 2008
¡´ Title: Techniques for Power Grid Analysis
Department of Applied Mathematics
National Chiao Tung University, November 29, 2007
¡´ Title: Power Delivery Network Analysis and Thermal Simulator
Techniques
MOE EDA Forum, Taiwan, March 3, 2006
¡@
Awards & Honors
¡´
Marquis Who¡¦s Who in the World, 2009 edition and selected for
2010 edition
¡´ Excellent Undergraduate Advisor, National Chiao Tung
University, 2008
¡´ The 1st Place, supervision for the IC/CAD Contest 2007 held by
Ministry of Education
(MOE), Taiwan.
¡´ ACM International Symposium on Physical Design Best Paper
Award, 2003
¡´ Harold A. Peterson First Place Graduate Student Paper Award,
Electrical and Computer
Engineering Department, University of Wisconsin-Madison, 2003
¡@
Publications
Journal
[1] Pei-Yu Huang and
Yu-Min Lee, ¡§Full-chip thermal analysis for the early design
stage via generalized integral transforms,¡¨ IEEE Transactions on
Very Large Scale Integration Systems, vol. 17, no. 5, pp.
613¡V626, May, 2009.
[2] Yu-Min Lee and Po-Yi Chiang, ¡§Effective sleep transistor
sizing algorithm for leakage power reduction,¡¨ to appear in
International Journal of Electrical Engineering, 2009.
[3] Pei-Yu Huang and Yu-Min Lee, ¡§Hierarchical power delivery
network analysis via bipartite Markov chains,¡¨ International
Journal of Electrical Engineering, vol. 16, no. 2, pp. 121¡V132,
May, 2009.
[4] Yu-Min Lee, Yahong
Cao, Tsung-Hao Chen, Janet Wang and Charlie Chung-Ping Chen, "HiPRIME:
Hierarchical and Passivity Preserved Interconnect Macromodeling
Engine for RLKC Power Delivery," IEEE Transactions on
Computer-Aided Design of Integrated Circuits And Systems (TCAD),
Vol. 24, No. 6, pp. 797-806, June, 2005.
[5] Yu-Min Lee and Charlie
Chung-Ping Chen, "The Power Grid Transient Simulation in Linear
Time Based on 3D Alternating-Direction-Implicit Method", IEEE
Trans. Computer-Aided Design of Integrated Circuits And Systems
(TCAD), Vol. 22, No. 11, pp. 1545-1550, November, 2003.
[6] Yu-Min Lee and Charlie
Chung-Ping Chen, "Power Grid Transient Simulation in Linear Time
Based on Transmission-Line-Modeling
Alternating-Direction-Implicit Method", IEEE Trans.
Computer-Aided Design of Integrated Circuits And Systems (TCAD),
Vol. 21, No. 11, pp. 1343 -1352, November, 2002.
[7] Yu-Min Lee, Charlie
Chung-Ping Chen, and D. F. Wong, "Optimal Wire-sizing Function
under the Elmore Delay Model with Bounded Wiresizes", IEEE
Trans. Circuits & Systems-I (TCAS-I) Vol. 49, No. 11, pp.
1671--1677, Nov. 2002.
[8] Yu-Min Lee, Charlie
Chung-Ping Chen, Yao-Wen Chang, and D. F. Wong,¡§Simultaneous
buffer-sizing and wire-sizing for clock trees based on
Lagrangian relaxation¡¨, VLSI Design Journal, vol. 15, no. 3, pp.
587-594, 2002.
[9] Ta-Sung Lee, Yu-min Lee,¡§Phase coherent blind equalization for high order QAM
signals¡¨, Journal of the Chinese Institute of Electrical
Engineering, vol.1, no.1, 1994.
International Conference
[1] Pei-Yu Huang, Jia-Hong
Wu, and Yu-Min Lee, ¡§Stochastic thermal simulation considering
spatial correlated within-die process variations,¡¨ Proc. of IEEE
Asia South Pacific Design Automation Conference, pp. 31¡V36,
January 2009.
[2] Shih-An Yu, Pei-Yu Huang, and Yu-Min Lee, ¡§A multiple supply
voltage based power reduction method in 3-D ICs considering
process variations and thermal effects,¡¨ Prof. of IEEE Asia
South Pacific Design Automation Conference, pp. 55¡V60, January
2009.
[3] Cheok-Kei Lei, Po-Yi Chiang, and Yu-Min Lee, ¡§Post-routing
redundant via insertion with wire spreading capability,¡¨ Proc.
of IEEE Asia South Pacific Design Automation Conference, pp.
468¡V473, January 2009.
[4] Jin-Tai Yan, Zhi-Wei Chen, Bo-Yi Chiang, and Yu-Min Lee,
¡§Timing-constrained yield-driven redundant via insertion,¡¨ Proc.
of IEEE Asia Pacific Conference on Circuits and Systems, pp.
1688¡V1691, December 2008.
[5] Pei-Yu Huang, Chih-Kang
Lin, and Yu-Min Lee, "Full-Chip Thermal Analysis for the Early
Design Stage via Generalized Integral Transforms", Asia South
Pacific Design Automation Conference (ASP-DAC) 2008.
[6] Pei-Yu Huang, Chih-Kang
Lin, and Yu-Min Lee, "Hierarchical Power Delivery Network
Analysis Using Markov Chains", IEEE International SOC Conference
(SOCC) 2007
[7] Yu-Min Lee, Huan-Yu
Chou, Pei-Yu Huang, "An Aggregation-based Algebraic Multigrid
Method for Power Grid Analysis", 8th International Symposium on
Quality Electronic Design (ISQED¡¦07)
[8] Pei-Yu Huang,Yu-Min
Lee, Jeng-Liang Tsai, and Charlie Chung-Ping Chen, "Simultaneous
area minimization and decaps insertion for power delivery
network using adjoint sensitivity analysis with IEKS method",
International Symposium on Circuits and Systems (ISCAS) 2006,
2006-05
[9] Ting-Yuan Wang, Yu-Min
Lee, and Charlie Chung-Ping Chen,¡§3D Thermal-ADI: an efficient
chip-level transient thermal simulator¡¨, International Symposium
on Physical Design (ISPD) 2003 (best paper award).
[10] Yu-Min Lee, Charlie
Chung-Ping Chen,¡§The power grid transient simulation in linear
time based on 3D alternating-direction-implicit method¡¨, Design,
Automation and Test in Europe (DATE) 2003.
[11] Yu-Min Lee, Charlie
Chung-Ping Chen,¡§A hierarchical analysis methodology for
chip-level power delivery with realizable model reduction¡¨, Asia
South Pacific Design Automation Conference (ASP-DAC) 2003.
[12] Yahong Cao, Yu-Min
Lee, Tsung-Hao Chen, and Charlie Chung-Ping Chen,¡§HiPRIME:
Hierarchical and passivity reserved interconnect macromodeling
engine for RLKC power delivery¡¨, Design Automation Conference (DAC)
2002.
[13] Yu-Min Lee, Charlie
Chung-Ping Chen,¡§Power grid transient simulation in linear time
based on transmission-line-modeling
alternating-direction-implicit method¡¨, International Conference
on Computer Aided Design (ICCAD) 2001.This work was cited by the
article "Analog modeling gets close but no cigar." in the
EETimes weekly, December 6,2001.
[14] Saisanthosh
Balakrishnan, Jong Hyuk Park, Hyungsuk Kim, Yu-Min Lee, and
Charlie Chung-Ping Chen,¡§Linear time hierarchical capacitance
extraction without multiple expansion¡¨, International Conference
on Computer Design (ICCD) 2001.
[15] Yu-Min Lee, Hing Yin
Lai, Charlie Chung-Ping Chen,¡§Optimal spacing and capacitance
padding for general clock structures¡¨, Asia South Pacific Design
Automation Conference (ASP-DAC) 2001.
[16] Yu-Min Lee, Charlie
Chung-Ping Chen,¡§Hierarchical model order reduction for
signal-integrity driven interconnect synthesis¡¨, Great Lake
Symposium on VLSI (GLSVLSI) 2000
Domestic Conference
[1] Huai-Chung Chang, Pei-Yu
Huang, Ting-Jung Li, and Yu-Min Lee, ¡§Thermal yield estimation
using statistical electro-thermal simulator,¡¨ Proc. of the 20th
VLSI Design/CAD Symposium, August 2009.
[2] Tsung-You Wu and Yu-Min Lee, ¡§Fast Legalize: Legalization
with minimal disturbance for standard cell design,¡¨ Proc. of the
20th VLSI Design/CAD Symposium, August 2009.
[3] Cheok-Kei Lei, Bo-Yi Chiang, and Yu-Min Lee, ¡§An efficient
redundant via insertion with wire pushing capability,¡¨ Proc. of
the 19th VLSI Design/CAD Symposium, August 2008.
[4] Shih-An Yu, Pei-Yu Huang, and Yu-Min Lee, ¡§Power
optimization in 3D ICs considering process variations and
thermal effect,¡¨ Proc. of the 19th VLSI Design/CAD Symposium,
August 2008.
[5] Pei-Yu Huang, Jia-Hong Wu, Yu-Min Lee, and Huai-Chung Chang,
¡§Stochastic thermal simulation considering with-in die process
variations,¡¨ Proc. of the 19th VLSI Design/CAD Symposium, August
2008.
[6] Huan-Yu Chou and Yu-Min Lee, ¡§An aggregation-based algebraic
multigrid method with application to on-chip power network
analysis,¡¨ Proc. of 16th VLSI Design/CAD Symposium, August 2005.
[7] Simon Yi-Hung Chen, Zhe-Yu Lin ,Yu-Min Lee,¡§LPGC : A Novel Low Power Driven
Placement Algorithm Based on Optimal Gated Clock Topology¡¨ in
Proceedings of the 16th VLSI Design/CAD Symposium, 2005.
[8] Yu-Min Lee, Jeng-Liang
Tsai, and Charlie Chung-Ping Chen, ¡§Simultaneous Area
Minimization and Decaps Insertion for Power Delivery Network
Using Adjoint Sensitivity Analysis with IEKS Method¡¨ in
Proceedings of the 14th VLSI Design/CAD Symposium, 2003.
International
Workshop
[1]
Pei-Yu Huang, Chih-Kang Lin,
and Yu-Min Lee, ¡§Full-chip thermal analysis via generalized
integral transforms,¡¨ Workshop on Synthesis and System
Integration of Mixed Information Technologies, pp 302¡V309,
October 2007.
[2] Yih-Lang Lin,
Pei-Yu Huang, Chih-Hong Hwang, and Yu-Min Lee, ¡§Performance-and
congestion-driven multilevel router,¡¨ Workshop on Synthesis and
System Integration of Mixed Information Technologies, pp.
439¡V445, April 2006.
[3] Pei-Yu
Huang, Chih-Hong Hwang, Po-Han Lai, and Yu-Min Lee,
¡§Hierarchical power deliver network analysis via bipartite
Markov chain,¡¨ Workshop on Synthesis and System Integration of
Mixed Information Technologies, pp. 189¡V196, April 2006.
[4] Cheng-Hsuan
Chiu, Yu-Chan Chang, Pei-Yu Huang, Chih-Hong Hwang, and Yu-Min
Lee, ¡§Crosstalk-driven placement with considering on-chip mutual
inductance and RLC noise,¡¨Workshop on Synthesis and System
Integration of Mixed Information Technologies, pp. 429¡V433,
April 2006.
¡@
Research
Project
Ongoing Projects
1. Process Variations Aware
Interconnect Modeling, Timing Analysis and Optimization (2/3)
(Amount: NTD$1,122,000; Aug. 2007 ~ Jul. 2008, NSC)
2. Compact Thermal Modeling and Efficient Thermal Simulation for
Hot Spots Verifications of Modern IC Designs (3/3) (Amount:
NTD$1,229,000; Aug. 2007 ~ Jul. 2008, NSC)
Completed Projects
1. Process Variations Aware Interconnect
Modeling, Timing Analysis and Optimization (1/3) (Amount:
NTD$1,107,000; Aug. 2006 ~ Jul. 2007, NSC)
2. Compact Thermal Modeling and Efficient
Thermal Simulation for Hot Spots Verifications of Modern IC
Designs (2/3) (Amount: NTD$1,229,000; Aug. 2006 ~ Jul. 2007, NSC)
3. Compact Thermal Modeling and Efficient
Thermal Simulation for Hot Spots Verifications of Modern IC
Designs (1/3) (Amount: NTD$1,076,000; Aug. 2005 ~ Jul. 2006, NSC)
4. Power Delivery Network Analysis with
Hierarchical Model Order Reduction Techniques (3/3) (Amount:
NTD$894,000; Aug. 2005 ~ Jul. 2006, NSC)
5. Power Delivery Network Analysis with
Hierarchical Model Order Reduction Techniques (2/3) (Amount:
NTD$882,000; Aug. 2004 ~ Jul. 2005, NSC)
6. Power Delivery Network Analysis with
Hierarchical Model Order Reduction Techniques (1/3) (Amount:
NTD$612,700; Nov. 2003 ~ Jul. 2004, NSC)
¡@
Advisees
Doctoral Student Advisees
Chi-Wen
Pan
2009¡Vpresent
Po-Yi Chiang
2007¡Vpresent
Pei-Yu Huang
2006¡Vpresent
Master
Student Advisees
Chih-Sheng
Wang 2009¡Vpresent
Shu-Han Whi
2008¡Vpresent
Ting-Jung Li
2008¡Vpresent
Chiao-Lin Cheng
2008¡Vpresent
Cheng-Chung Chien
2005¡Vpresent
Masters
Degree Research Supervisor
Huai-Chung
Chang
¡§An electro-thermal simulator considering process variations
with high compatibility of power model¡¨, 2009
Tsung-You Wu
¡§FastLegalize: Legalization for standard cell based design with
minimal disturbance¡¨, 2009 Shian-Je Shiu ¡§A novel and fast sleep
transistor sizing algorithm by using integral sensitivity¡¨, 2009
Bing-Hsing Su
¡§Bootstrap confidence intervals as an approach to model
within-die spatial correlation under process variations¡¨, 2009,
currently working for TSMC
Cheok-Kei Lei
¡§An efficient redundant via insertion method with wire pushing
capability¡¨, 2008, currently working for TSMC
Shih-An Yu
¡§Power optimization in 3D ICs considering process variations and
thermal effect¡¨, 2008, currently working for Synopsys Taiwan
Jia-Hong Wu
¡§Stochastic thermal simulation considering within-die spatial
correlation under process variations¡¨, 2007, currently working
for TSMC
Zhe-Yu Lin
¡§A multilevel low power clock network driven placement¡¨, 2006,
currently working for Synopsys Taiwan
Huan-Yu Chou
¡§An aggregation-based algebraic multigrid method with
application to on-chip power distribution network analysis¡¨,
2006, currently working for Faraday Technology
Chen-Hsuan Chiu
¡§Crosstalk-driven placement with on-chip mutual inductance and
RLC noise considerations¡¨, 2005, currently working for ITRI
Electronics Research & Service Organization
Yih-Lang Lin
¡§Performance- and congestion- driven multilevel router¡¨, 2005,
currently working for eMemory Technology
Yi-Hung Chen
¡§LPGC: A novel low power driven placement algorithm based on
optimal gated clock topology¡¨, 2005, currently working for
SpringSoft Inc.
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Summary
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