Chip-level thermal analysis（晶片系統之熱傳分析）
With the rapid evolution of today's deep micron technology, the shrinking of the process line width and the increase in the number of integrated wafer layers make the design of the wafer more complicated and difficult. The evolution of technology is accompanied by an increase in power, current density, and operating frequency, and many parasitic effects, leakage currents, and reliability issues become very important, with one of the most serious problems of heat dissipation.
As the size of the component shrinks and the power per unit area increases, the heat generated by the wafer per unit area increases exponentially, and the temperature-related parameters affecting all the wafers further lead to problems such as IR-Drop, leakage current, and electromigration. The problem will be further affected by the performance of the entire system, such as Delay, clock skew and so on. In the worst case, the entire wafer will burn out in an instant and even cause damage to the related system and loss of property. Therefore, the thermal analysis and simulation of the complete wafer, the thermal correlation reliability problem, and the heat-oriented wafer design will be a very important part in the future system chip design, so we will focus on this aspect of the wafer system design automation tool with development and research.
System-level thermal analysis and design for handheld devices（系統層級熱傳分析及設計應用於手持裝置）
While smartphones become more and more powerful, the power consumed in SoCs increases dramatically. Their performance is often limited by thermal constraints. Though the capability of passive cooling system for heat removal is usually insufficient, unfortunately, active cooling techniques are not suitable for handheld devices. Therefore, thermal behaviors in handheld devices should be well-considered during design stages.
For passive cooling techniques, the heat flow in handheld devices is mainly dissipated by two heat transfer modes, free convection (natural convection) and thermal radiation. Free convection is a fluid motion mechanism due to the density gradient. The warm air with lower density rises and the cool air falls down through buoyancy force and gravity. Through the air flow induced by natural convection, the heat has been taken away from the heat source. Thermal radiation is another heat dissipation mechanism that happens on the situation that the object temperature is greater than absolute zero. Thermal radiation is energy released by the oscillations of electrons in matter, that is, the heat is dissipated by electromagnetic wave emission. As pointed out in “Fundamentals of heat and mass transfer” (F. P. Incropera et al.), the heat transfer mechanism of free convection and thermal radiation is temperature dependent, which should be included in thermal analysis.
Process variation aware statistical timing analysis & optimization (考量製程變異性下之統計型時序分析技術與最佳化)
With the advancement of complementary metal oxide semiconductor (CMOS) process technology, the transmission delay of components has dropped significantly and the transmission delay of internal wiring has risen; the propagation delay of wires has dominated the performance of circuits and it is designed in very large integrated circuit designs. The importance of this continues to rise. However, when the process technology reaches the nano stage, the process variation caused by the manufacturing process will seriously affect the reliability of the wire. Based on this consideration, to achieve high reliability and to ensure that the design specifications meet the requirements, a precise and considerable process variation wire model is indispensable. Timing is one of the most important issues, especially for optimizing critical paths, reducing wire transmission delays, clock skew, and even suppressing crosstalk noise. Meanwhile, timing plays an important role.
Under the consideration of process variation factors, the wire model suitable for time series analysis is explored and developed, and the existing time series analysis methods are deeply studied to develop a set of time series analysis and optimization tools considering process variation. In the early stages of the project, we will study the effects of process variation on the timing reliability of the wire; for example, crosstalk noise, rough surface, and chemical mechanical polishing (CMP) timing. The influence on it. In addition, we will develop a series of wire models and timing analysis methods that consider process variables using existing wire models and timing analysis methods. Then, through the model reduction technique, an accurate and fast statistical timing analysis tool was developed. Finally, the project uses a technique of simultaneously adjusting the wire, logic gate size, and buffer placement to propose and implement a timing optimization tool based on geometric planning and considering process variation to construct the optimal timing key. Path, reduce delay on the wire, and at the same time achieve acceptable missed noise.
Power delivery network analysis and optimization（晶片系統之電力傳輸分析技術及最佳化設計）
As the complexity of very large integrated circuit (VLSI) wafers increases, wafers require large amounts of metal resources as a medium for power transmission. The number of wires will exceed 100 million segments in the nano design, which will make power transmission design and analysis a challenging task. Poor power transmission network design will reduce circuit performance, noise margin, and reliability.
In order to confirm the design quality of power transmission, transient power transmission simulation must be used to analyze the fluctuation of power transmission. However, due to the large matrix of analysis circuits, traditional circuit simulation tools such as SPICE/HSPICE will not be able to effectively analyze such systems, and will require a very large amount of memory and several days to complete the simulation. In addition, given the type of power transmission network, there are a number of techniques that can be used to improve the quality of power transmission systems, such as changing the width of a wire or adding a back-coupling capacitor. Changing the size of the wire is a very effective method for reducing power fluctuations and enhancing electron migration. However, unrestricted increase in wire width can take up too much routing resources. Therefore, it is necessary to reduce the area of the power network. Therefore, one of our research directions is to develop effective power transmission analysis and design tools.
Circuit design techniques for driving RLC interconnect (RLC Interconnect驅動之電路設計技術)
In deep sub-micron CMOS circuits, the impedance of the interconnect is one of the main causes of delay between signals. The interaction between active CMOS components and passive wiring is one of the most important issues in the design of high-performance ultra-large integrated circuit systems. And the long connection line structure for transmitting high-speed signals can be appropriately modeled into an RLC transmission line model. Therefore, the focus of this research is to establish a representation of the closed solution and correct analysis of the CMOS circuit and the load impedance of the load on the transistor, and then correctly describe the relationship between them. This representation method can be applied to the development of ultra-large integrated circuit design methods driven by RC and RLC line impedance.