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        Journal
  1. Yu-Min Lee and Chia-Tung Ho, “InTraSim: Incremental Transient Simulation of Power Grids”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 36, no. 12, pp 2052~2065, December 2017.

  2. Yu-Min Lee, Kuan-Te Pan, and Chun Chen, “NaPer: A TSV Noise-Aware Placer”, IEEE Transactions on Very Large Scale Integration Systems (TVLSI), vol.25, no. 5, pp. 1703~1713, May 2017.

  3. Hong-Wen Chiou, Yu-Min Lee, “Thermal Simulation for Two-Phase Liquid Cooling 3D-ICs”, Journal of Computer and Communications, vol. 4, no. 15, pp. 33~45, November 2016.

  4. Yu-Min Lee, Chi-Wen Pan, Pei-Yu Huang, and Chi-Ping Yang, “LUTSim: A Look-Up Table Based Thermal Simulator for 3-D ICs”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 34, no. 8, pp. 1250~1263, August 2015.

  5. Yu-Min Lee and Pei-Yu Huang, “An Efficient Method for Analyzing the On-Chip Thermal Reliability with Considering Process Variations”, ACM Transactions on Design Automation of Electronic Systems (TODAES), vol. 18, no. 2, article no. 41, July 2013.

  6. Yu-Min Lee and Chi-Wen Pan, “Redundant Via Insertion with Wire Spreading Capability”, International Journal of Electrical Engineering (IJEE), vol. 17, no. 6, pp.383-398, December 2010.

  7. Yu-Min Lee and Po-Yi Chiang, “Effective sleep transistor sizing algorithm for leakage power reduction”, International Journal of Electrical Engineering (IJEE), vol. 16, no. 5, pp. 421-431, October 2009.

  8. Pei-Yu Huang and Yu-Min Lee, “Hierarchical Power Delivery Network Analysis via Bipartite Markov Chains”, International Journal of Electrical Engineering (IJEE), vol. 16, no. 2, pp. 121-132, May 2009.

  9. Pei-Yu Huang and Yu-Min Lee, “Full-chip thermal analysis for the early design stage via generalized integral transforms”, IEEE Transactions on Very Large Scale Integration Systems, vol. 17, no. 5, pp. 613–626, May, 2009.

  10. Yu-Min Lee, Yahong Cao, Tsung-Hao Chen, Janet Wang and Charlie Chung-Ping Chen, “HiPRIME: Hierarchical and Passivity Preserved Interconnect Macromodeling Engine for RLKC Power Delivery”, IEEE Transactions on Computer-Aided Design of Integrated Circuits And Systems (TCAD), Vol. 24, No. 6, pp. 797-806, June, 2005.

  11. Yu-Min Lee and Charlie Chung-Ping Chen, “The Power Grid Transient Simulation in Linear Time Based on 3D Alternating-Direction-Implicit Method”, IEEE Trans. Computer-Aided Design of Integrated Circuits And Systems (TCAD), Vol. 22, No. 11, pp. 1545-1550, November, 2003.

  12. Yu-Min Lee and Charlie Chung-Ping Chen, “Power Grid Transient Simulation in Linear Time Based on Transmission-Line-Modeling Alternating-Direction-Implicit Method”, IEEE Trans. Computer-Aided Design of Integrated Circuits And Systems (TCAD), Vol. 21, No. 11, pp. 1343 -1352, November, 2002.

  13. Yu-Min Lee, Charlie Chung-Ping Chen, and D. F. Wong, “Optimal Wire-sizing Function under the Elmore Delay Model with Bounded Wiresizes”, IEEE Trans. Circuits & Systems-I (TCAS-I) Vol. 49, No. 11, pp. 1671--1677, Nov. 2002.

  14. Yu-Min Lee, Charlie Chung-Ping Chen, Yao-Wen Chang, and D. F. Wong,“Simultaneous buffer-sizing and wire-sizing for clock trees based on Lagrangian relaxation”, VLSI Design Journal, vol. 15, no. 3, pp. 587-594, 2002.

  15. Ta-Sung Lee, Yu-min Lee,“Phase coherent blind equalization for high order QAM signals”, Journal of the Chinese Institute of Electrical Engineering, vol.1, no.1, 1994.

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     International Conference
  1. Wen-Sheng Lo, Hong-Wen Chiou, Shih-Chieh Hsu, Yu-Min Lee, and Liang-Chia Cheng, “Learning based mesh generation for thermal simulation in handheld devices with variable power consumption,” in The Intersociety Conference on Thermal and Theromechanical Phenomena in Electronic System (ITherm), 2019. (slides)

  2. Hong-Wen Chiou, Yu-Min Lee, Shin-Yu Shiau, Chi-Wen Pan, Tai-Yu Chen, “Phone-nomenon: A system-level thermal simulator for handheld devices,” in Asia South Pacific Design Automation Conference (ASPDAC), 2019. (slides) (Best Paper Nominee)

  3. Hsuan-Hsuan Hsiao, Hong-Wen Chiou, Yu-Min Lee, “Multi-angle bended heat pipe design using X-architecture routing with dynamic thermal weight on mobile devices,” in Asia South Pacific Design Automation Conference (ASPDAC), 2019. (slides)

  4. Jui-Hung Wang, Yu-Min Lee, Hsuan-Hsuan Hsiao, and Liang-Chia Cheng, “A system-level thermal simulator with automatic meshing techniques,” in The Intersociety Conference on Thermal and Theromechanical Phenomena in Electronic System (ITherm), 2018.

  5. Hong-Wen Chiou, Yu-Min Lee, Hsuan-Hsuan Hsiao, Liang-Chia Cheng, “Thermal modeling and design on smartphones with heat pipe cooling technique,” in International Conference on Computer Aided Design (ICCAD), 2017. (slides)

  6. Yu-Min Lee, Chi-Han Lee, Yan-Cheng Zhu, “Yield-Driven Redundant Power Bump Assignment for Power Network Robustness,” in Asia South Pacific Design Automation Conference (ASPDAC), 2017.

  7. Hong-Wen Chiou, Yu-Min Lee, “Thermal Simulation for Two-Phase Liquid Cooling 3D-ICs,” in International Conference on Computer Simulation, Graphics and Aided Design (CSGAD), 2016.

  8. JiaXing Song, Yu-Min Lee, Chia-Hung Ho, “ThermPL: Thermal-aware Placement Based on Thermal Contribution and Locality,” in International Symposium on VLSI Design and Test (VLSI-DAT), 2016.

  9. Yu-Min Lee, Chun Chen, JiaXing Song, Kuan-Te Pan, “A TSV Noise-Aware 3-D Placer,” in The Design, Automation, and Test in Eurpoe Conference (DATE), 2015.

  10. Chia Tung Ho, Yu-Min Lee, Shu-Han Wei, Liang-Chia Cheng, “Incremental Transient Simulation of Power Grid,”in International Symposium on Physical Design (ISPD), 2014. (slides)

  11. Chia-Tung Ho, Yu-Min Lee, “Efficient Transient Incremental Analysis of On-Chip Power Grid,” in Asia-Pacific Radio Science Conference (AP-RASC), 2013. (invited)

  12. Shu-Han Wei, Yu-Min Lee, Chia-Hung Ho, Chih-Ting Sun, Liang-Chia Cheng, “Power Delivery Network Design for Wiring and TSV Resource Minimization in TSV-Based 3-D ICs,” in International Symposium on VLSI Design and Test (VLSI-DAT), 2013.

  13. Yu-Min Lee, Tsung-Heng Wu, Pei-Yu Huang, Chi-Ping Yang, "NUMANA: A Hybrid Numerical and Analytical Thermal Simulator for 3-D ICs," in The Design, Automation, and Test in Eurpoe Conference (DATE), 2013. (slides)

  14. Chi-Wen Pan, Yu-Min Lee, Pei-Yu Huang, Chi-Ping Yang, Chang-Tzu Lin, Chia-Hsin Lee, Yung-Fa Chou, Ding-Ming Kwai, "I-LUTSim: An Iterative Look-Up Table Based Thermal Simulator for 3-D ICs,"  Asia South Pacific Design Automation Conference (ASPDAC), 2013. (slides) (Best Paper Award)

  15. Yi-Hsuan Lee, Yu-Min Lee, Liang-Chia Cheng, Yen-Tang Chang, "A Robust Incremental Power Grid Analyzer by Macromodeling Approach and Orthogonal Matching Pursuit," Asia Symposium on Quality Electronic Design (ASQED), 2012.

  16. Pei-Yu Huang, Yu-Min Lee, and Chi-Wen Pan “On-Chip Statistical Hot-Spot Estimation Using Mixed-Mesh Statistical Polynomial Expressing Generating and Skew-Normal Based Moment Matching Techniques,” in Asia South Pacific Design automation Conference (ASPDAC), 2012.

  17. Shu-Han Wei, Yu-Min Lee, “Supply Voltage Assignment for Power Reduction in 3D ICs Consudering Thermal Effect and Level Shifter Budget,” in International Symposium on VLSI Design and Test (VLSI-DAT), 2011.

  18. Chi-Wen Pan and Yu-Min Lee, “Redundant via insertion under timing constraints,” in International Symposium on Quality Electronic Design (ISQED), 2011.
  19. Huai-Chung Chang, Pei-Yu Huang, Ting-Jung Li, and Yu-Min Lee, “Statistical Electro-Thermal Analysis with High Compatibility of Leakage Power Models”, in International SoC Conference (SOCC 2010).

  20. Shu-Han Wei, Bing-Shiun Su, Yu-Min Lee, and Chi-Wen Pan, “Spatial Correlation Extraction with a Limited Amount of Measurement Data”, in Asia Symposium on Quality Electronic Design (ASQED) 2010.

  21. Yu-Min Lee, Tsung-You Wu, and Po-Yi Chiang,“A Hierarchical Bin-Based Legalizer for Standard-Cell Designs with Minimal Disturbance”, in Asia South Pacific Design Automation Conference (ASPDAC), pp. 568-573, 2010. (slides)

  22. Pei-Yu Huang, Jia-Hong Wu and Yu-Min Lee, Stochastic Thermal Simulation Considering Spatial Correlated Within-Die Process Variations, Asia South Pacific Design Automation Conference (ASPDAC), pp. 31-36, 2009.

  23. Shih-An Yu, Pei-Yu Huang and Yu-Min Lee, A Multiple Supply Voltage Based Power Reduction Method In 3-D ICs Considering Process Variations And Thermal Effects, Asia South Pacific Design Automation Conference (ASPDAC), pp. 55-60, 2009.

  24. Cheok-Kei Lei, Po-Yi Chiang and Yu-Min Lee, Post-Routing Redundant Via Insertion With Wire Spreading Capability, Asia South Pacific Design Automation Conference (ASPDAC), pp. 468-473,  2009.

  25. Jin-Tai Yan, Zhi-Wei Chen, Bo-Yi Chiang, and Yu-Min Lee, Timing-Constrained Yield-Driven Redundant via Insertion, Asia Pacific Conference on Circuits and Systems (APCCAS), pp. 1688-1691, 2008.

  26. Pei-Yu Huang, Chih-Kang Lin, and Yu-Min Lee, Full-Chip Thermal Analysis for the Early Design Stage via Generalized Integral Transforms, Asia South Pacific Design Automation Conference (ASPDAC), pp. 462-467, 2008.

  27. Pei-Yu Huang, Chih-Kang Lin, and Yu-Min Lee, Hierarchical Power Delivery Network Analysis Using Markov Chains, IEEE International SOC Conference (SOCC), pp. 283-286, 2007.

  28. Yu-Min Lee, Huan-Yu Chou, Pei-Yu Huang, An Aggregation-based Algebraic Multigrid Method for Power Grid Analysis, 8th International Symposium on Quality Electronic Design (ISQED’07)

  29. Pei-Yu Huang,Yu-Min Lee, Jeng-Liang Tsai, and Charlie Chung-Ping Chen, Simultaneous area minimization and decaps insertion for power delivery network using adjoint sensitivity analysis with IEKS method, International Symposium on Circuits and Systems (ISCAS) 2006, 2006-05

  30. Ting-Yuan Wang, Yu-Min Lee, and Charlie Chung-Ping Chen, “3D Thermal-ADI: an efficient chip-level transient thermal simulator”, International Symposium on Physical Design (ISPD) 2003 (Best Paper Award).

  31. Yu-Min Lee, Charlie Chung-Ping Chen, “The power grid transient simulation in linear time based on 3D alternating-direction-implicit method”, Design, Automation and Test in Europe (DATE) 2003.

  32. Yu-Min Lee, Charlie Chung-Ping Chen, “A hierarchical analysis methodology for chip-level power delivery with realizable model reduction”, Asia South Pacific Design Automation Conference (ASPDAC) 2003.

  33. Yahong Cao, Yu-Min Lee, Tsung-Hao Chen, and Charlie Chung-Ping Chen,“HiPRIME: Hierarchical and passivity reserved interconnect macromodeling engine for RLKC power delivery”, Design Automation Conference (DAC) 2002.

  34. Yu-Min Lee, Charlie Chung-Ping Chen,“Power grid transient simulation in linear time based on transmission-line-modeling alternating-direction-implicit method”, International Conference on Computer Aided Design (ICCAD) 2001.This work was cited by the article Analog modeling gets close but no cigar. in the EETimes weekly, December 6,2001.

  35. Saisanthosh Balakrishnan, Jong Hyuk Park, Hyungsuk Kim, Yu-Min Lee, and Charlie Chung-Ping Chen,“Linear time hierarchical capacitance extraction without multiple expansion”, International Conference on Computer Design (ICCD) 2001.

  36. Yu-Min Lee, Hing Yin Lai, Charlie Chung-Ping Chen,“Optimal spacing and capacitance padding for general clock structures”, Asia South Pacific Design Automation Conference (ASPDAC) 2001.

  37. Yu-Min Lee, Charlie Chung-Ping Chen,“Hierarchical model order reduction for signal-integrity driven interconnect synthesis”, Great Lake Symposium on VLSI (GLSVLSI) 2000.

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     Domestic Conference
  1. Huai-Chung Chang, Pei-Yu Huang, Ting-Jung Li, and Yu-Min Lee, “Thermal yield estimation using statistical electro-thermal simulator, ” Proc. of the 20th VLSI Design/CAD Symposium, August 2009.

  2. Tsung-You Wu and Yu-Min Lee, “Fast Legalize: Legalization with minimal disturbance for standard cell design,” in Proc. of the 20th VLSI Design/CAD Symposium, August 2009.

  3. Cheok-Kei Lei, Bo-Yi Chiang and Yu-Min Lee,“An Efficient Redundant Via Insertion with Wire Pushing Capability” in Proceedings of the 19th VLSI Design/CAD Symposium, 2008.

  4. Shih-An Yu, Pei-Yu Huang and Yu-Min Lee,“Power Optimization in 3D ICs Considering Process Variations and Thermal Effect” in Proceedings of the 19th VLSI Design/CAD Symposium, 2008.

  5. Pei-Yu Huang, Jia-Hong Wu, Yu-Min Lee, and Huai-Chung Chang,“Stochastic Thermal Simulation Considering With-in Die Process Variations” in Proceedings of the 19th VLSI Design/CAD Symposium, 2008.

  6. Huan-Yu Chou and Yu-Min LeeAn Aggregation-Based Algebraic Multigrid Method with Application to On-Chip Power Network Analysis in Proceedings of the 16th VLSI Design/CAD Symposium, 2005.

  7. Simon Yi-Hung Chen, Zhe-Yu Lin ,Yu-Min Lee, “LPGC : A Novel Low Power Driven Placement Algorithm Based on Optimal Gated Clock Topology” in Proceedings of the 16th VLSI Design/CAD Symposium, 2005.

  8. Yu-Min Lee, Jeng-Liang Tsai, and Charlie Chung-Ping Chen, “Simultaneous Area Minimization and Decaps Insertion for Power Delivery Network Using Adjoint Sensitivity Analysis with IEKS Method” in Proceedings of the 14th VLSI Design/CAD Symposium, 2003.

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     International Workshop

  1. Pei-Yu Huang, Chih-Kang Lin, and Yu-Min Lee, Full-Chip Thermal Analysis via Generalized Integral Transforms, The 14th Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI) 2007, 2007-10.

  2. Yih-Lang Lin, Pei-Yu Huang, Chih-Hong Hwang, and Yu-Min Lee, “Performance- and congestion-driven multilevel router”, The 13th Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI) 2006, 2006-04.

  3. Pei-Yu Huang, Chih-Hong Hwang, Po-Han Lai, and Yu-Min Lee, “Hierarchical Power Deliver Network Analysis Via Bipartite Markov Chain”, The 13th Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI) 2006, 2006-04.

  4. Cheng-Hsuan Chiu, Yu-Chan Chang, Pei-Yu Huang, Chih-Hong Hwang, Yu-Min Lee,  “Crosstalk-Driven Placement with Considering On-Chip Mutual Inductance and RLC Noise”,   Proceeding of the Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI) 2006.

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